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Example Schematic
This appendix provides an example schematic for an FT 6000 Smart Transceiver. The
example schematics are based on the FT 6000 Evaluation Board that is included with the FT
6000 Evaluation Kit. The example schematic incorporates the design requirements that are
described in the following sections:
• On-Chip Memory
• Memory Map
• External Serial Memory Interface
• Pin Connections
• Connection for an FT 6000 Smart Transceiver
• Clock Requirements
• Transformer Electrical Connections
Basic Electrical Connections
Figure 60 shows the basic electrical connections for the FT 6000 Smart Transceiver.
SVC
-
C22
100pF
0603
NO LD
12
C21
100pF
0603
NO LD
12
VDD_3
V3
VDD_3V3
TCK_X
R12 4.99K 1%
0603
1 2
R13 49.9 1%
0603
1 2
TCK
C11
0.
1uF
10%
X7R
16V
0603
1
2
C1
0.1uF
10%
X7R
16V
0603
12
C2
0
.1uF
10
%
X7R
16V
0603
12
CS_2
_SC
L
V
DD1
V8
C
S_1_
SDA
R
19 200 1%
0603
1 2
XOUT
XOUT
_R
L2
0.5A 0603
150
1 2
MISO
IO2
IO1
S
CLK
IO0
L1
0.5A
0603
150
1 2
IO3
C12
33pF
5%
NPO
50V
0603
12
VDD1
V8
C13
33pF
5%
NPO
50V
0603
12
MOSI
IO6
IO5
VDD_3V3
IO4
IO7
IO8
IO
11
I
O10
I
O9
U1
FT
5000
QFN
48 Pads
Echelon
SVC-
1
IO0
2
IO1
3
IO2
4
IO3
5
VDD1V
8
6
IO
4
7
VDD
3V3
8
IO5
9
IO6
10
IO7
11
IO
8
12
I
O9
13
IO1
0
1
4
IO1
1
15
VDD1
V8
16
TR
ST-
1
7
VD
D3V
3
1
8
TCK
1
9
T
MS
20
T
DI
2
1
T
DO
22
X
I
N
23
XOUT
2
4
VDDPLL
25
GNDPLL
26
VOUT1V8
27
RST-
28
VIN3V3
29
VDD3V3
30
AVDD3V3
31
NETN
32
AGND
33
NETP
34
NC
35
GND
36
TX
ON
37
RXO
N
38
CP4
3
9
CS0
-
40
VDD
3V3
41
VD
D3V
3
4
2
S
DA_
CS1
-
43
V
DD1
V8
44
SCL
4
5
M
ISO
4
6
SC
K
4
7
M
OSI
4
8
GN
D P
AD
49
V
DD_
3V3
T
RST
-
VDD
1V8
TMS
TCK
VDD_3V3
C
P2_
TXLE
DXO
UT
X
I
N
TDO
TDI
C3
0
.1uF
10
%
X7R
16V
0603
12
C10
0.01uF
10
%
X7R
50V
0603
12
C4
0.1uF
10%
X7
R
16V
0603
12
VDD1V8
NETP
_CP
1
NC1
C6
1.0uF
10%
X7R
16V
0603
12
FT 6000
C8
0.1uF
10%
X7R
16V
0603
12
NETN_CP0
C9
0.1uF
10%
X7R
16V
0603
1
2
Y1
10.0000MHZ
1
3
2
4
CP4
CP
3_
R
X
L
ED
R15 1M 5
%
0603
1 2
C
S
_0
_S
P
I
VD
D_3V
3
XIN
XOUT
D3B
BAV99
75V
3 2
D3A
BAV99
75V
1
3
D4B
BAV99
75V
3 2
D4A
BAV99
75
V
1
3
VDD
_3V3
VDD
_3V3
RST-
C5
0
.1uF
10
%
X7
R
16V
0603
12
C7
0.
1uF
10%
X7R
16V
0603
12
RST-
VDD
_3V
3
XIN
VDD1V8
SVC-
PLLVSSA
PLLVDDA
Figure 60. Basic Electrical Connections
156 Handling and Manufacturing Guidelines
- Series 6000 1
- Chip Data 1
- Welcome 3
- Audience 3
- Neuron Chips 3
- Related Documentation 4
- ONWORKS devices and 5
- Table of Contents 8
- Introduction 13
- Product Family Overview 14
- FT 6000 Smart Transceiver 14
- Neuron 6000 Processor 14
- ONWORKS Networks 15
- Transceivers 20
- Specification Summaries 21
- Hardware Resources 25
- Series 6000 Architecture 26
- Multiple Processors 29
- Interrupts 31
- Assembly Instruction Set 31
- Memory Architecture 35
- On-Chip Memory 36
- Memory Map 36
- Device Support 40
- Device Programming 41
- Recovering a Device 41
- Transience 42
- Data Logging 42
- Boot Loader 42
- JTAG Interface 43
- Operating Conditions 44
- ))1012(( 45
- Pin Assignments 46
- Neuron 6000 49
- Processor 49
- Pin Connections 51
- Smart Transceiver 52
- 6000 Processor 56
- Single-Ended Mode 58
- Special-Purpose Mode 62
- TPT/XF-1250 Transceivers 69
- EIA-485 Transceivers 70
- GROUND GUARD 72
- Reset Function 75
- RST~ Pin 75
- Reset Sources 76
- Power-Up and LVI 77
- Watchdog Timer 77
- Software-Controlled Reset 78
- Reset Processes and Timing 78
- SVC~ Pin 81
- Integrity Mechanisms 82
- Processor Integrity 82
- System Firmware Image 82
- PC Board Layout Guidelines 86
- Host Microprocessor 88
- (optional) 88
- Power Supply 88
- Circuitry 88
- I/O Circuitry 88
- Design and Test for 89
- Achieving High Immunity 91
- Electrostatic Discharge 91
- Transceiver 93
- +3.3 V Output 94
- Dressler 96
- Alpha 250 / 75W 96
- ATT 6 / 75 96
- Surge and Burst 97
- Lightning Protection 98
- Network Line Protection 98
- Shield Protection 98
- Summary and Testing Results 101
- Network Connection 104
- Network Topology Overview 104
- System Specifications 107
- Overview 112
- Two 16-Bit Timer/Counters 112
- Hardware Considerations 121
- Programming Considerations 125
- Development Hardware Setup 126
- Release Hardware Setup 127
- SNMP Support 128
- Supported Commands 128
- Supported Objects 128
- Connections 134
- Checklist 4: Power Supply 136
- Qualified TP/FT-10 Cable 141
- Specifications 141
- Qualified Cables 142
- FT-X3 Communications 147
- Transformer 147
- Top View 148
- Schematic View 148
- ONWORKS 149
- Transformer pad 151
- Handling and Manufacturing 153
- Guidelines 153
- Application Considerations 154
- Termination of Unused Pins 154
- Decoupling Capacitors 158
- Recommended Solder Profile 158
- Example Schematic 167
- Basic Electrical Connections 168
- Memory Interface Connections 169
- Transformer Connections 169
- I/O and Network Connections 169
- BOM for Example Schematic 170
- Vendor Contact Information 172
- Vendor Information 173
- Abracon Corporation 173
- Atmel Corporation 173
- Belden Inc 173
- BPM Microsystems 174
- Citel Inc 174
- CommScope Inc 174
- Emulation Technology Inc 175
- Fairchild Semiconductor Inc 175
- Laird Technologies PLC 176
- Littelfuse Inc 176
- Numonyx BV 176
- NXP Semiconductors BV 177
- ON Semiconductor 177
- Panasonic Corp 177
- Sankosha Corp 178
- Taiyo Yuden Company Ltd 179
- TDK Corp 179
- Total Phase Inc 179
- Vishay Intertechnology Inc 180
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