Echelon Series 6000 Chip databook Bedienungsanleitung Seite 9
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- Inhaltsverzeichnis
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Comparison with FT 3120 or FT 3150 Devices ............................. 55
Comparison with Series 5000 Devices ........................................... 56
Comparison with the FTT-10A Transceiver .................................. 56
Connection for a Neuron 6000 Processor ............................................. 57
TPT/XF-1250 Transceivers ............................................................. 57
EIA-485 Transceivers ..................................................................... 58
LPT-11 Link Power Transceivers .................................................. 59
Clock Requirements ..................................................................................... 61
External Crystal .................................................................................... 61
Comparison with Series 3100 Clocks ................................................... 62
Reset Function.............................................................................................. 63
RST~ Pin ................................................................................................ 63
Reset Sources ......................................................................................... 64
Power-Up and LVI .......................................................................... 65
Watchdog Timer .............................................................................. 65
Traps ................................................................................................ 66
Software-Controlled Reset .............................................................. 66
Reset Processes and Timing ................................................................. 66
SVC~ Pin ...................................................................................................... 69
Integrity Mechanisms .................................................................................. 70
Processor Integrity ................................................................................ 70
System Firmware Image ....................................................................... 70
Application Integrity Using Checksums .............................................. 70
Hardware Design Considerations ............................................................... 73
PC Board Layout Guidelines ....................................................................... 74
Design and Test for Electromagnetic Compatibility ............................. 77
Overview ....................................................................................................... 78
Achieving High Immunity ........................................................................... 79
Electrostatic Discharge ................................................................................ 79
Electromagnetic Interference ...................................................................... 80
Radiated and Conducted Immunity ............................................................ 82
Surge and Burst ........................................................................................... 85
Lightning Protection .................................................................................... 86
Building Entrance Protection ............................................................... 86
Network Line Protection ....................................................................... 86
Shield Protection ................................................................................... 86
Suggested Gas Discharge Arresters ..................................................... 86
Avoiding Magnetic Field Interference ........................................................ 88
Summary and Testing Results .................................................................... 89
Network Cabling and Connections for FT Devices ................................ 91
Network Connection .................................................................................... 92
Network Topology Overview ....................................................................... 92
System Performance and Cable Selection .................................................. 94
System Specifications ............................................................................ 95
Transmission Distance Specifications .................................................. 95
Cable Termination and Shield Grounding ................................................. 96
Free Topology Network Segment ......................................................... 96
Doubly Terminated Bus Topology Segment ........................................ 96
Grounding Shielded Twisted Pair Cable .............................................. 97
Input/Output Interfaces for the Series 6000 ............................................ 99
Overview ..................................................................................................... 100
Series 6000 Chip Data Book ix
- Series 6000 1
- Chip Data 1
- Welcome 3
- Audience 3
- Neuron Chips 3
- Related Documentation 4
- ONWORKS devices and 5
- Table of Contents 8
- Introduction 13
- Product Family Overview 14
- FT 6000 Smart Transceiver 14
- Neuron 6000 Processor 14
- ONWORKS Networks 15
- Transceivers 20
- Specification Summaries 21
- Hardware Resources 25
- Series 6000 Architecture 26
- Multiple Processors 29
- Interrupts 31
- Assembly Instruction Set 31
- Memory Architecture 35
- On-Chip Memory 36
- Memory Map 36
- Device Support 40
- Device Programming 41
- Recovering a Device 41
- Transience 42
- Data Logging 42
- Boot Loader 42
- JTAG Interface 43
- Operating Conditions 44
- ))1012(( 45
- Pin Assignments 46
- Neuron 6000 49
- Processor 49
- Pin Connections 51
- Smart Transceiver 52
- 6000 Processor 56
- Single-Ended Mode 58
- Special-Purpose Mode 62
- TPT/XF-1250 Transceivers 69
- EIA-485 Transceivers 70
- GROUND GUARD 72
- Reset Function 75
- RST~ Pin 75
- Reset Sources 76
- Power-Up and LVI 77
- Watchdog Timer 77
- Software-Controlled Reset 78
- Reset Processes and Timing 78
- SVC~ Pin 81
- Integrity Mechanisms 82
- Processor Integrity 82
- System Firmware Image 82
- PC Board Layout Guidelines 86
- Host Microprocessor 88
- (optional) 88
- Power Supply 88
- Circuitry 88
- I/O Circuitry 88
- Design and Test for 89
- Achieving High Immunity 91
- Electrostatic Discharge 91
- Transceiver 93
- +3.3 V Output 94
- Dressler 96
- Alpha 250 / 75W 96
- ATT 6 / 75 96
- Surge and Burst 97
- Lightning Protection 98
- Network Line Protection 98
- Shield Protection 98
- Summary and Testing Results 101
- Network Connection 104
- Network Topology Overview 104
- System Specifications 107
- Overview 112
- Two 16-Bit Timer/Counters 112
- Hardware Considerations 121
- Programming Considerations 125
- Development Hardware Setup 126
- Release Hardware Setup 127
- SNMP Support 128
- Supported Commands 128
- Supported Objects 128
- Connections 134
- Checklist 4: Power Supply 136
- Qualified TP/FT-10 Cable 141
- Specifications 141
- Qualified Cables 142
- FT-X3 Communications 147
- Transformer 147
- Top View 148
- Schematic View 148
- ONWORKS 149
- Transformer pad 151
- Handling and Manufacturing 153
- Guidelines 153
- Application Considerations 154
- Termination of Unused Pins 154
- Decoupling Capacitors 158
- Recommended Solder Profile 158
- Example Schematic 167
- Basic Electrical Connections 168
- Memory Interface Connections 169
- Transformer Connections 169
- I/O and Network Connections 169
- BOM for Example Schematic 170
- Vendor Contact Information 172
- Vendor Information 173
- Abracon Corporation 173
- Atmel Corporation 173
- Belden Inc 173
- BPM Microsystems 174
- Citel Inc 174
- CommScope Inc 174
- Emulation Technology Inc 175
- Fairchild Semiconductor Inc 175
- Laird Technologies PLC 176
- Littelfuse Inc 176
- Numonyx BV 176
- NXP Semiconductors BV 177
- ON Semiconductor 177
- Panasonic Corp 177
- Sankosha Corp 178
- Taiyo Yuden Company Ltd 179
- TDK Corp 179
- Total Phase Inc 179
- Vishay Intertechnology Inc 180
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